图书简介：  本书以FPGA/CPLD设计流程为主线，阐述了如何合理利用ISE设计平台集成的各种设计工具，高效地完成FPGA/CPLD的设计方法与技巧。全书在介绍FPGA/CPLD概念和设计流程的基础上，依次论述工程管理与设计输入、仿真、综合、约束、实现与布局布线、配置调试等主要设计步骤在ISE集成环境中的实现方法与技巧。 本书立足工程实践，结合作者多年工作经验，选用大量典型实例，并配有一定数量的练习题。本书配套光盘收录了所有实例的完整工程目录、源代码、详细操作步骤和使用说明，利于读者边学边练，提高实际应用能力。 本书可作为高等院校通信工程、电子工程、计算机、微电子与半导体学等专业的教材，也可作为硬件工程师和IC工程师的实用工具书。

《FPGA/CPLD 设计工具——Xilinx ISE5.X 使用详解》图书目录如下：

目      录  第1章　ISE系统简介　1                                      1.1　FPGA/CPLD简介　1                                      1.1.1　FPGA/CPLD的基本原理　2                                      1.1.2　FPGA/CPLD的特点　2                                      1.2　FPGA/CPLD的设计流程　3                                      1.3　ISE系列产品的新特点　5                                      1.3.1　特点综述　5                                      1.3.2　ISE  5.x的新增特性　6                                      1.4　ISE  5.x支持的器件　8                                      1.5　ISE  5.x的系统配置与安装　9                                      1.5.1　推荐的系统配置　9                                      1.5.2　ISE  5.x的安装　10                                      1.6　ISE  5.x的集成工具及其基本功能　12                                      1.7　常用专有名词解释　15                                      1.8　小结　17                                      1.9　问题与思考　18                                      第2章    工程管理器与设计输入工具　19                                      2.1　ISE工程管理器──Project  Navigator　19                                      2.1.1　Project  Navigator综述　19                                      2.1.2　Project  Navigator的用户界面　20                                      2.1.3　使用Project  Navigator创建并管理工程　27                                      2.2　HDL语言的输入工具──HDL  Editor　32                                      2.2.1　HDL  Editor综述　32                                      2.2.2　源代码输入的好助手──Language  Templates　32                                      2.3　状态机输入工具──StateCAD　34                                      2.3.1　StateCAD综述　34                                      2.3.2　StateCAD的用户界面　35                                      2.3.3　使用StateCAD设计状态机　40                                      2.4　原理图输入工具──ECS　51                                      2.4.1　ECS综述　52                                      2.4.2　ECS的用户界面　52                                      2.4.3　使用ECS完成原理图输入设计　55                                      2.4.4　使用ECS进行混合设计的方法　62                                      2.5　IP核生成工具──CORE  Generator　63                                      2.5.1　CORE  Generator综述　63                                      2.5.2　CORE  Generator的用户界面　64                                      2.5.3　使用CORE  Generator生成IP核的方法与技巧　67                                      2.6　测试激励生成器──HDL  Bencher　72                                      2.6.1　HDL  Bencher综述　72                                      2.6.2　使用HDL  Bencher生成测试激励　74                                      2.7　设计结构向导──Architecture  Wizard　80                                      2.7.1　Architecture  Wizard综述　80                                      2.7.2　Architecture  Wizard使用方法　80                                      2.8　小结　83                                      2.9　问题与思考　83                                      第3章　ModelSim仿真工具　85                                      3.1　ModelSim的用户接口　86                                      3.2　ModelSim仿真窗口综述　88                                      3.3　仿真环境的建立　94                                      3.3.1　仿真库的命名　95                                      3.3.2　仿真库文件的手动建立　96                                      3.4　一个简单的仿真示例　97                                      3.4.1　在ModelSim环境下进行仿真　97                                      3.4.2　在ISE集成环境中进行仿真　100                                      3.5　混合VHDL/Verilog仿真　102                                      3.6　ModelSim中的调试方法　104                                      3.7　使用批处理方式进行仿真　107                                      3.8　波形比较与WLF文件　109                                      3.8.1　创建一个参考的数据集合　109                                      3.8.2　修改源文件重新运行仿真　110                                      3.8.3　进行波形比较　110                                      3.9　SDF时序标注　115                                      3.10    仿真中的代码覆盖率　116                                      3.11    VCD文件　118                                      3.11.1　创建VCD文件　118                                      3.11.2　使用一个VCD文件重新进行仿真　119                                      3.12    问题与思考　120                                      第4章　ISE中集成的综合工具　121                                      4.1　新兴的高效综合工具──Synplify/Synplify  Pro　121                                      4.1.1　Synplify/Synplify  Pro  的功能与特点　121                                      4.1.2　Synplify  Pro的用户界面　126                                      4.1.3　Synplify  Pro综合流程　130                                      4.1.4　Synplify  Pro的其他综合技巧　146                                      4.2　Xilinx最早的合作伙伴──Synopsys综合工具　158                                      4.2.1　设计流程　159                                      4.2.2　FE综合优化过程　161                                      4.2.3　FST操作说明　170                                      4.3　Xilinx内嵌的综合工具──XST　173                                      4.3.1　XST综述　173                                      4.3.2　XST综合属性设置　173                                      4.3.3　使用XST的综合流程　178                                      4.4　全局时钟与第二全局时钟资源　182                                      4.4.1　全局时钟资源简介　182                                      4.4.2　常用的与全局时钟资源相关的Xilinx器件原语　182                                      4.4.3　Xilinx全局时钟资源的使用方法　185                                      4.4.4　使用Xilinx全局时钟资源的注意事项　186                                      4.4.5　第二全局时钟资源　188                                      4.5　小结　189                                      4.6　问题与思考　189                                      第5章　约束　191                                      5.1　概述　191                                      5.2　时序约束　193                                      5.2.1　周期约束（PERIOD约束）　193                                      5.2.2　偏移约束（OFFSET约束）　196                                      5.2.3　专门约束　199                                      5.3　分组约束　202                                      5.3.1　TNM约束　202                                      5.3.2　TNM_NET约束　205                                      5.3.3　TIMEGRP约束　205                                      5.3.4　TPTHRU约束　206                                      5.3.5　TPSYNC约束　206                                      5.4　约束编辑器──Constraints  Editor　207                                      5.4.1　Constraints  Editor的用户界面　207                                      5.4.2　附加全局约束　208                                      5.4.3　附加端口约束　210                                      5.4.4　附加分组约束和时序约束　211                                      5.4.5　附加专用约束　214                                      5.5　引脚与区域约束编辑器──PACE　215                                      5.5.1　PACE的用户界面　216                                      5.5.2　附加区域约束　219                                      5.5.3　附加I/O引脚约束　220                                      5.6　约束文件　221                                      5.6.1　约束文件的概念　221                                      5.6.2　UCF.  NCF文件的基本语法规则　222                                      5.7　小结　224                                      5.8　问题与思考　224                                      第6章　辅助设计工具　225                                      6.1　时序分析器──Timing  Analyzer　225                                      6.1.1　时序分析器的用户界面　226                                      6.1.2　时序分析器的作用及设计流程　227                                      6.1.3　基本时序路径　228                                      6.1.4　时序分析器的使用方法　236                                      6.2　布局规划器──Floorplanner　240                                      6.2.1　布局规划器的用户界面　240                                      6.2.2　布局规划器的特点及作用　242                                      6.2.3　布局规划设计流程　243                                      6.2.4　设计示例　246                                      6.3　FPGA底层编辑器──FPGA  Editor　251                                      6.3.1　FPGA底层编辑器的用户接口　251                                      6.3.2　FPGA底层编辑器的作用　252                                      6.3.3　FPGA底层编辑器输入输出文件　254                                      6.3.4　FPGA底层编辑器的工作流程　255                                      6.3.5　使用FPGA底层编辑器的预备知识　255                                      6.3.6　设计示例　257                                      6.4　小结　262                                      6.5　问题与思考　262                                      第7章　XPower.  iMPACT和ChipScope  Pro　263                                      7.1　XPower　263                                      7.1.1　XPower综述　263                                      7.1.2　XPower的用户界面　264                                      7.1.3　用XPower分析功耗　267                                      7.2　iMPACT　269                                      7.2.1　iMPACT综述　269                                      7.2.2　iMPACT的用户界面　270                                      7.2.3　用iMPACT下载配置文件　273                                      7.3　ChipScope  Pro　281                                      7.3.1　ChipScope  Pro综述　281                                      7.3.2　ChipScope  Pro  Core  Inserter　283                                      7.3.3　ChipScope  Pro  Analyzer　289                                      7.4　小结　294                                      7.5　问题与思考　294                                      第8章　模块化设计方法　295                                      8.1　模块化设计方法的基本概念　295                                      8.2　模块化设计方法的设计流程　296                                      8.2.1　Modular  Design的设计输入与综合步骤　297                                      8.2.2　Modular  Design的实现步骤　298                                      8.3　模块化设计方法的注意事项与设计技巧　302                                      8.3.1　Modular  Design的目录管理　302                                      8.3.2　Modular  Design的常用约束　303                                      8.3.3　Modular  Design的设计规模与性能表现　303                                      8.3.4　Modular  Design的报告查看　304                                      8.3.5　使用XFLOW自动进行模块化设计　304                                      8.4　模块化设计方法的设计实例　306                                      8.5　小结　315                                      8.6　问题与思考　316                                      第9章　融会贯通──“运动计时表”设计　317                                      9.1　示例背景　318                                      9.2　多元混合设计输入方法　319                                      9.2.1　新建工程“watch_sc　319                                      9.2.2　使用ECS绘制“cnt60”和“outs3”模块原理图　320                                      9.2.3　使用Core  Generator生成“tenthsIP核　326                                      9.2.4　使用StateCAD设计“stmach_v”状态机　329                                      9.2.5　使用Architecture  Wizard生成时钟管理模块“dcm1　337                                      9.2.6　使用语言模板设计“hex2led”和“decode”的HDL源代码　339                                      9.2.7　使用ECS设计顶层原理图　342                                      9.3　测试激励与行为级功能仿真　343                                      9.3.1　使用HDL  Bencher生成测试激励　344                                      9.3.2　调用ModelSim进行行为级功能仿真　346                                      9.4　Synplify  Pro和XST综合方法　347                                      9.4.1　使用XST综合整个设计　348                                      9.4.2　使用Synplify  Pro的特色工具分析.  优化设计　350                                      9.5　设计用户约束文件与实现结果的分析　356                                      9.5.1　使用Constraints  Editor设计UCF文件　356                                      9.5.2　使用PACE设计UCF　359                                      9.5.3　实现步骤与实现结果分析　361                                      9.6　使用ModelSim进行布线后仿真　366                                      9.7　使用iMPACT配置FPGA/CPLD　367                                      9.8　小结　372                                      9.9　问题与思考　372