例如：

always @(count)
   case (count) 
   2'h0: next_count = 2'h1;
   2'h1: next_count = 2'h2;
   2'h2: next_count = 2'h3;
   2'h3: next_count = 2'h0;
   endcase
end

always @ (posedge clk or posedge reset)
begin
  if (reset) begin
    count = 0;
  end
  else if (enable) begin
    count = next_count;
  end
end

另一种方法是异步产生计数使能，条件是使能信号必须没有毛刺并且与时钟信号有恰当的定时关系。

例如：

wire gate_clk = clk & enable;

always @ (posedge gate_clk or posedge reset)
begin
  if (reset) begin
    count = 0;
  end
  else begin
    count = count + 1;
  end
end

另一种类型的计数器是波纹计数器。这种计数器适合速度较慢、要求低功耗的场合，可以用Verilog很容易地实现。

例如：

always @(count) begin
   count0 = count[0] ;
   count1 = count[1] ;
   count2 = count[2] ;
end

always @(posedge clk or posedge reset) begin
  if (reset) begin
    count[0] = 0 ;
  end
  else begin
    count[0] = ~count[0];
  end
end

always @(posedge count0 or posedge reset)
begin
  if (reset) begin
    count[1] = 0 ;
  end
  else begin
    count[1] = ~count[1];
  end
end

always @(posedge count1 or posedge reset)
begin
  if (reset) begin
    count[2] = 0 ;
  end
  else begin
    count[2] = ~count[2];
  end
end

always @(posedge count2 or posedge reset)
begin
  if (reset) begin
    count[3] = 0 ;
  end
  else begin
    count[3] = ~count[3];
  end
end